1. Field of the Invention
This invention relates to a semiconductor integrated circuit device and more particularly to a semiconductor integrated circuit device in which a measure to counter soft errors is taken.
2. Description of the Related Art
As the generation proceeds, the transistor size becomes smaller and the size of the latch circuit becomes smaller. Therefore, in the latch circuit, soft errors, for example, soft errors caused by α rays become significant. As one countermeasure against occurrence of the soft error, a method for increasing the storage node capacity of the latch circuit is provided. However, this method has a disadvantage that the size of the latch becomes large.
The soft error also occurs in the memory cell of the semiconductor memory, for example, in the memory cell of an SRAM. In the present semiconductor memory, an array (which is hereinafter referred to as a parity data portion) in which memory cells used to store data for error detection/correction, for example, parity data are arranged is additionally provided in addition to an array (which is hereinafter referred to as a normal data portion) in which memory cells used to store normal data are arranged. This is a so-called semiconductor memory with an ECC function. The semiconductor memory with the ECC function is described in Jpn. Pat. Appln. KOKAI Publication No. 2003-59290, for example.
However, when α rays are applied to the parity data portion to cause soft errors, it becomes impossible to determine whether data held in the normal data portion is true or not. Further, it is impossible to determine whether the soft error is generated in the normal data portion or in the parity data portion.